1) DRAM Capacity & Bandwidth Assume a processor with 3 DDR DRAM channels of width 64 bit, operating at 1.4 GHz. All channels support up to 4 ranks of DIMMs. A DIMM contains multiple chips with the following properties. Banks have 8K rows and 256 columns. A DRAM chip has 8 banks and an x4 interface with a burst rate of 16. a) How many bits does each column store? (2 Points) b) What is the capacity of a single chip? (2 points) c) What is the capacity of a DIMM? (Please state your assumption of ranks per DIMM) (2 Points) d) What is the maximum DRAM capacity supported by the processor? (2 Points) e) What is the maximum memory bandwidth that the system supports? (2 Points) Show transcribed image text 1) DRAM Capacity & Bandwidth Assume a processor with 3 DDR DRAM channels of width 64 bit, operating at 1.4 GHz. All channels support up to 4 ranks of DIMMs. A DIMM contains multiple chips with the following properties. Banks have 8K rows and 256 columns. A DRAM chip has 8 banks and an x4 interface with a burst rate of 16. a) How many bits does each column store? (2 Points) b) What is the capacity of a single chip? (2 points) c) What is the capacity of a DIMM? (Please state your assumption of ranks per DIMM) (2 Points) d) What is the maximum DRAM capacity supported by the processor? (2 Points) e) What is the maximum memory bandwidth that the system supports? (2 Points)