(Solved): Part III Figure 2a shows a circuit for a full adder, which has the inputs a, b, and G. and produces ...

Part III Figure 2a shows a circuit for a full adder, which has the inputs a, b, and G. and produces the outputs s and co- Parts and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sumcos= a +b+. Figure 2d shows how four instances of this full adder module can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of the way that the carry signals are passed from one full adder to the next. Write Verilog code that implements this circuit, as described below. FA 6 5 a) Full adder circuit b) Full adder symbol 5 b; ay sy boa 00 01 0 1 10 0 1 10 10 FA FA FA 000 001 010 011 100 101 110 111 FA Cout c) Full adder truth table d) Four-bit ripple-carry adder circuit Figure 2: A ripple-carry adder circuit. 1. Create a new Quartus project for the adder circuit. Write a Verilog module for the full adder subcircuit and write a top-level Verilog module that instantiates four instances of this full adder. 2. Use switches SW-4 and SW3-0 to represent the inputs A and B. respectively. Use SW for the carry-in Gin of the adder. Connect the outputs of the adder. Cout and S, to the red lights LEDR. 3. Include the necessary pin assignments for the DEI-SoC board, compile the circuit, and download it into the FPGA chip 4. Test your circuit by trying different values for numbers A. B, and in