(Solved): Please help me with this MIPSassignment!1. (10 points) Consider the 5-stage MIPS pipeline architectu ...

Please help me with this MIPSassignment!

1. (10 points) Consider the 5-stage MIPS pipeline architecture. (figure shown below) Each stage of MIPS pipeline takes 1 cycle. We assume no branch prediction, no forwarding. The processor hazard detection logic stalls the pipeline in order to avoid hazard We also assume all instruction/data memory access can be completed within 1 cycle. PCSro WB EXMEM MEMWB EX WB IFAD Add Branch left 2 u PC register 1 data 1 register 2 ALU ALU Registers Read data 2 Write [15-0] 16 Sign- 32 20-16] ALUOp [15-11 If a sequence of instructions has no pipeline hazard, the pipeline will be fully utilized. For example, LW r3, 0x100 (r4)I r3 <- mem[ex100+ r4] ADD r8 , r2, r10 / / r8 ?-r2 + r10 will take 7 cycles (-52), because there is no data/control dependency and the pipeline is fully utilized. But if there are data/control dependencies, the pipeline needs to stall and thus execution of the instructions will take longer. For example, ADD OR r7, r2, r10 r6, r7, r18 // r7 <- r2+ r10 // r6 ?-r7 | r18 will take 9 cycles, because r7 creates RAW hazard in this case, causing the pipeline to stall 3 cycles. (Stalling is needed because we need to wait ADD instruction to complete WB stage before OR starts ID stage.) Another example: LW r5, ex100 (r4) I/ r5 <- mem[0x100 r4] ADD r8, r5, r1e // r8 <- r5 + r10 will also take 9 cycles due to r5 RAW dependency. Yet another example: (assume r7 is 0 at start) BEQ ADD OR AND r7, re, label branch to label if r70 r8, r5, r10 r6, r10, r18 r16, r11, r12 r21, r28, 0x4 r5, 0x100 (r4) // r5 <- mem [0x100 r4] // r8 <- r5 + r10 label: ADDI // r21 <- r28 + 4 LW will take 10 cycles due to branch taken. (ADDI can only start at cycle 5 as BEQ's branch decision updates PC at cycle 4.) Question: determine the number of cycles needed to finish following code sequences (a) (2 points) ADD ADD ADD SUB SUB OR r2, r9, r10 r4, r2, r10 r6, r4, r10 r11, r22, r10 r13, r11, r10 r20, r26, r2711 r20 <- r26 | r27 / r2 <- r9 r10 r4 <- r2 r10 / r6 <- r4 r10 // r11 <- r22 -r10 // r13 <- r11 - r10 (b) (2 points) ADD SUB SUB ADD ADD OR r2, r9, r10 r1l, r22, r10 r13, r11, r10 r4, r2, r10 r6, r4, r10 r20, r26, r2711 r20 <- r26 | r27 / r2 <- r9 r10 // r11 ?-r22 - r10 / r13 <- r11 - r10 // r4?-r2 + r18 // r6 <- r4 + r10 (c) (2 points) ADD SUB OR ADD SUB ADD r2, r9, r10 r11, r22, r10 r20, r26, r27 r4, r2, r10 r13, r11, r10 r6, r4, r10 // r2?-r9 + r10 // r11 <- r22- r10 /1 r20 <- r26 | r27 // r4?-r2 + r18 // r13 <- r11 - r10 // r6??r4 + r18 (d) (2 points) Assume r7 is 0x77 at start ADDI BEQ ADD OR AND r7, r7,-0x77 r7, re, label// branch to label if r70 r8, r5, r10 r6, r1e, r18 r16, r11, r12 r21, r28, 0x4 r5, 0x100 (r4) 1/ r5 <- mem[ex100 r4] //#7?-r7-ex77 // r8?-r5 + r10 label: ADDI //r21?-r28 + 4 LW (e) (2 points) Assume r7 is 0x77 at start) //#7?-r7-ex77 ADDI r7, r7, -0x77 ADD OR BEQ r7, re, label ANDr16, r11, r12 // r8 <- r5 r10 // branch to label if r70 //r21?-r28 + 4 r8, r5, r10 r6, r1e, r18 label: ADDI r21, r28, 0x4 LW r5, 0x100 (r4) // r5 <- mem[0x100 r4] We were unable to transcribe this imageShow transcribed image text 1. (10 points) Consider the 5-stage MIPS pipeline architecture. (figure shown below) Each stage of MIPS pipeline takes 1 cycle. We assume no branch prediction, no forwarding. The processor hazard detection logic stalls the pipeline in order to avoid hazard We also assume all instruction/data memory access can be completed within 1 cycle. PCSro WB EXMEM MEMWB EX WB IFAD Add Branch left 2 u PC register 1 data 1 register 2 ALU ALU Registers Read data 2 Write [15-0] 16 Sign- 32 20-16] ALUOp [15-11
If a sequence of instructions has no pipeline hazard, the pipeline will be fully utilized. For example, LW r3, 0x100 (r4)I r3